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1 features q > 400.0 mbps ( 200 mhz) switching rates q + 340mv differential signaling q 3.3 v power supply q ttl compatible outputs q cold spare all pins q ultra low power cmos technology q 4.0 ns maximum propagation delay q 0.35 ns maximum differential skew q radiation-hardened design; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 3 00 krad(si) and 1mrad(si) - latchup immune (let > 1 00 mev-cm 2 /mg) q packaging options: - 16-lead flatpack (dual in-line) q standard microcircuit drawing 5962-98652 - qml q and v compliant part introduction the ut54 lvds032lv q uad receiver is a quad cmos differential line receiver designed for applications requiring ultra low power dissipation and high data rates. the device is designed to support data rates in excess of 400.0 mbps ( 200 mhz) utilizing low voltage differential signaling (lvds) technology. the ut54 lvds032lv a ccepts low voltage (340mv) differential input signals and translates them to 3v cmos o utput levels. the receiver supports a three-state function that may be used to multiplex outputs. the receiver also supports open, shorted and terminated (100 w ) input fail-safe. receiver output will be high for all fail-safe conditions. the ut54 lvds032lv a nd companion quad line driver ut54 lvds031lv p rovides new alternatives to high power pseudo-ecl devices for high speed point-to-point interface applications. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . standard products ut54lvds032lv low voltage q uad receiver data sheet may, 2003 figure 1. ut54 lvds032lv q uad receiver block diagram + r1 - r in1+ r in1- r in2+ r in2- r in3+ r in3- r in4+ r in4- r out1 r out2 r out4 r out3 en en + r 2 - + r 3 - + r 4 -
2 truth table pin description applications information the ut54 lvds032lv r eceiver?s intended use is primarily in an uncomplicated point-to-point configuration as is shown in figure 3. this configuration provides a clean signaling environment for quick edge rates of the drivers. the receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply pcb traces. typically, the characteristic impedance of the media is in the range of 100 w . a termination resistor of 100 w should be selected to match the media and is located as close to the receiver input pins as possible. the termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account. the ut54 lvds032lv d ifferential line receiver is capable of detecting signals as low as 100mv, over a + 1v common-mode range centered around +1.2v. this is related to the driver offset voltage which is typically +1.2v. the driven signal is centered around this voltage and may shift + 1v around this center point. the + 1v shifting may be the result of a ground potential difference between the driver?s ground reference and the receiver?s ground reference, the common-mode effects of coupled noise or a combination of the two. both receiver input pins should honor their specified operating input voltage range of 0v to +2.4v (measured from each pin to ground). enables input output en en r in+ - r in - r out l h x z all other combinations of enable inputs v id > 0.1v h v id < -0.1v l full fail-safe open/short or terminated h pin no. name description 2, 6, 10, 14 r in+ non-inverting receiver input pin 1, 7, 9, 15 r in- inverting receiver input pin 3, 5, 11, 13 r out receiver output pin 4 en active high enable pin, or-ed with en 12 en active low enable pin, or-ed with en 16 v dd power supply pin, + 3.3 + 0.3v 8 v ss ground pin figure 2 . ut54 lvds032lv p inout ut54 lvds032lv receiver 16 15 14 13 12 11 10 9 v dd r in4- r in4+ r out4 en r out3 r in3+ r in3- 1 r in1- 2 r in1+ 3 r out1 4 en 5 r out2 6 r in2+ 7 r in2- 8 v ss enable data input 1/4 ut54lvds031lv 1/4 ut54lvds032lv + - data output figure 3. point-to-point application rt 100 w
3 receiver fail-safe the ut54 lvds032lv r eceiver is a high gain, high speed device that amplifies a small differential signal (20mv) to ttl l ogic levels. due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. the receiver?s internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection (a stable known state of high output voltage) for floating, terminated or shorted receiver inputs. 1. open input pins . the ut54 lvds032lv i s a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left open. do not tie unused receiver inputs to ground or any other voltages. the input is biased by internal high value pull up and pull down resistors to set the output to a high state. this internal circuitry will guarantee a high, stable output state for open inputs. 2. terminated input . if the driver is disconnected (cable unplugged), or if the driver is in a three-state or power- off condition, the receiver output will again be in a high state, even with the end of cable 100 w termination resistor across the input pins. the unplugged cable can become a floating antenna which can pick up noise. if the cable picks up more than 10mv of differential noise, the receiver may see the noise as a valid signal and switch. to insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. twisted pair cable offers better balance than flat ribbon cable. 3. shorted inputs . if a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0v differential input voltage, the receiver output remains in a high state. shorted input fail-safe is not supported across the common-mode range of the device (v ss to 2.4v). it is only supported with inputs shorted and no external common-mode voltage applied.
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and l ife test . 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0. 3 t o 4 .0v v i/o voltage on any pin during operation -0.3 to (v dd + 0.3v) voltage on any pin during cold spare -.3 to 4.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1 .25 w t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6 v t c case temperature range - 55 to +125 c v in dc input voltage , receiver inputs dc input voltage, logic inputs 2.4v 0 to v dd for en, en
5 dc electrical characteristics 1 (v dd = 3.3 v + 0.3v ; -55 c < t c < +125 c) notes: 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenc ed to ground. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. only one output should be shorted at a time, do not excee d maximum junction temperature specification. 3. guaranteed by characterization. symbol parameter condition min max unit v ih high-level input voltage ( ttl) 2.0 v v il low-level input voltage ( ttl) 0 . 8 v v o l low-level output voltage i ol = 2m a, v dd = 3.0 v 0. 25 v v oh high-level output voltage i oh = -0.4ma, v dd = 3.0 v 2.7 v i in logic in put leakage current enables = en/ en = 0 and 3.6 v, v dd = 3.6 -10 +10 m a i i receiver in put current v in = 2.4v -15 +15 ma i cs cold spare leakage current v in =3.6v, v dd =v ss -20 +20 ma v th 3 differential input high threshold v cm = +1.2v +100 mv v tl 3 differential input low threshold v cm = +1.2v -100 mv i o z 3 output three-state current disabled, v out = 0 v or v dd -10 +10 ma v cl input clamp voltage i cl = + 18ma -1.5 v i os 2, 3 output short circuit current enabled, v out = 0 v 2 -1 5 -130 ma i cc 3 s upply current , receivers enabled en, en = v dd o r v ss inputs ope n 1 5 ma i ccz 3 s upply current , receivers disabled en = v ss , en = v dd inputs open 4 ma
6 ac switching characteristics 1, 2, 3 (v dd = + 3.3 v + 0.3v, t a = -55 c to +125 c) notes: 1. channel-to-channel skew is defined as the difference between the propagation delay of the channel and the other channels in t he same chip with an event on the inputs. 2. generator waveform for all tests unless otherwise specified: f = 1 mhz, z 0 = 50 w , t r and t f (0% - 100%) < 1ns for r in and t r and t f < 1ns for en or en . 3. c l includes probe and jig capacitance. 4. guaranteed by characterization. 5. chip to chip skew is defined as the difference between the minimum and maximum specified differential propagation delays. 6. may be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter. symbol parameter min max unit t phld 6 differential propagation delay high to low cl = 1 0pf (figures 4 and 5) 1. 0 4.0 ns t plhd 6 differential propagation delay low to high cl = 1 0pf (figures 4 and 5) 1. 0 4.0 ns t skd 4 differential skew (t phld - t plhd ) (figures 4 and 5) 0 0.35 ns t sk 1 4 channel-to-channel skew 1 (figures 4 and 5) 0 0.5 ns t sk 2 4 ch ip -to-ch ip skew 5 ( figures 4 and 5) 1.5 ns t tlh 4 rise time (figures 4 and 5) 1.2 ns t thl 4 fall time (figures 4 and 5) 1.2 ns t phz 4 disable time high to z (figures 6 and 7) 12 ns t plz 4 disable time low to z (figures 6 and 7) 12 ns t pzh 4 enable time z to high (figures 6 and 7) 12 ns t pzl 4 enable time z to low (figures 6 and 7) 12 ns
7 r r in+ r out receiver enabled generator 50 w figure 4. receiver propagation delay and transition time test circuit or equivalent circuit r in- 50 w 10pf r in- r in+ r out t phld v ol v oh +1.1v 50% +1.2v t thl 20% 80% 50% 20% 80% t tlh 0v differential figure 5. receiver propagation delay and transition time waveforms t plhd v id = 200mv +1.3v
8 figure 6. receiver three-state delay test circuit or equivalent circuit r in+ r in- en v dd 2k 2k 10pf en when en = v dd en when en = v ss output when v id = -100mv output when v id = +100mv t phz t pzh 0.5v 50% v oh v oz v oz 0v v dd 0v v dd 1.5v 1.5v 1.5v 1.5v 0.5v t pzl t plz figure 7. receiver three-state delay waveform 50% v ol
9 notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance to mil-prf-38535. 4. package dimensions and symbols are similar to mil-std-1835 variation f-5a. 5. lead position and coplanarity are not measured. 6. id mark symbol is vendor option. 7. with solder, increase maximum by 0.003. figure 8. 16-pin ceramic flatpack packaging
10 ordering information ut54 lvds032lv q uad receiver: ut 54lvds032lv - * * * * * device type: ut54 lvds032lv l vds receiver access time: not applicable package type: (u) = 16-lead flatpack (dual-in-line) screening: (c) = military temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
11 ut54 lvds032lv q uad receiver: smd 5962 - * * * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) (g) = 5e5 rad(si) (h) = 1e6 rad(si) drawing number: 5962-98652 device type 02 = lvds receiver, 300k, 500k and 1m rad(si) 03 = lvds receiver, 100k rad(si) class designator: (q) = qml class q (v) = qml class v case outline: (y ) = 16 lead flatpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) ** 98652 notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.

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